Nanditha Rao

Assistant Professor

Phone: 918041407777


  • Ph.D. (Indian Institute of Technology, Bombay)

Nanditha Rao obtained her B.E in Electronics & Communication Engineering from PES Institute of Technology, Bangalore and PhD in Electrical Engineering from Indian Institute of Technology, Bombay, India. Prior to joining the PhD programme, she worked as a Hardware design engineer (Signal Integrity) at Intel Technologies, Bangalore for a period of  six years.

At Intel, she was responsible for signal integrity simulations of motherboard interconnects, interacted with customers on design guidelines and specialized in buffer modeling.  She was selected to be part of a 4-member team representing Intel, to talk about Intel next-generation platform overview to 16 Intel customers in Asia Pacific region. This was part of the customer tour to ODMs/OEMs in Korea, Taiwan and Japan in Nov-Dec 2006. 
She received 13 ‘spontaneous recognition awards’ and one ‘divisional recognition award’ at Intel.

She was awarded the “Institute Organizational Citation” at IIT Bombay. This is awarded to graduating students in recognition of the contribution to institute's organizational activities during the entire stay in the institute.

Her research interests are in the area of computer architecture: Cache compression, FPGA based system designs, design to overcome security issues and radiation tolerant/hardened designs. She plans to explore the area of machine learning hardware accelerators, prefetching and technology which could be used in rural areas. 

Link to the Resume


Research Interests

  • Radiation-hardened/Fault tolerant circuit design, Computer architecture - cache compression, processor security, branch predictors

Selected Publications

Pls refer to Link to the Resume, for the latest updates.

  • Nanditha P. Rao, Madhav P. Desai, “Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology,” Microelectronics Journal, Volume 72, 2018, Pages 86-99
  • N. P. Rao and M. P. Desai, "A Detailed Characterization of Errors in Logic Circuits due to Single-Event Transients," Digital System Design (DSD), 2015 Euromicro Conference, Funchal, 2015, pp. 714-721. doi: 10.1109/DSD.2015.58
  • Poster Presentation: Nanditha P Rao, Shahbaz Sarik and Madhav P Desai,“On the likelihood of multiple bit upsets in logic circuits”, VLSI Design Conference 2014, Mumbai, India.
  • Presentation: Reed Nelson, Sara Stille, Nanditha Rao, Steve Hall, Scott Gilbert, Tony Lewis, Tal Israeli, ‘Impact of halogen free stackup on Pcie signaling’ in the PCI-SIG conference in Santaclara, June 2010.
  • Presentation: Nanditha Rao, “De-emphasis buffer modeling issues with IBIS”, in the Asian IBIS Summit, Tokyo, Nov 2008. (
  • Presentation: Nanditha Rao, Sara Stille, “Signal integrity challenges and design practices on a mobile platform” in the PCI-SIG conference in Munich, Nov 2007.
  • T. N. Ruckmongathan, Nanditha Rao P., and Ankita Prasad, “Wavelets for Displaying Gray Shades in LCDs”, SID (Society of Information Display) Symposium Digest of Technical Papers, May 2005, USA, Volume 36, Issue 1, pp. 168-171.


ESD: 803- Processor architecture (iMTech/MTech elective: Spring semester)

  • Evolution of processors, evaluating processor's performance,  
  • Data and control path
  • Instruction set architecture, instruction execution
  • Pipelining, pipeline hazards
  • Data forwarding and branch prediction
  • Instruction level parallelism, speculation, multiple issue processors, out of order execution
  • Memory hierarchy, caches, replacement policies and improving cache performance

EG 201- Computer architecture (iMTech core course: Fall semester- 3rd semester)

  • Computer components, bus interconnections
  • Integer arithmetic
  • Instruction set architecture, addressing modes
  • Intro to 8085 and programming the peripherals
  • Memory- DRAM, caches, virtual memory
  • I/O and interrupts
  • Example processor studies: Intel Pentium and ARM Cortex

Research & Consulting

Currently advising 2 MS(Research) students

other Information

Office: 133-E

Extension number: 163