At the High Density Electronic Systems Lab at IIIT-Bangalore, we focus on research and development in the area of Low power VLSI circuits, interconnects, approximate computing design, and optimization techniques of digital VLSI circuits.

HiDES is affiliated to Center of Electronics and Embedded systems lab (CEEMS) and Computational Sciences Lab (CSL) at IIITB. The HiDES lab at IIITB is sponsored by Government of Karnataka, and Mentor Graphics Corporation LTD. Projects running in HiDES lab is sponsored by SERB, MEITY, MSJE, IBM Shared University Research, INTEL-FICE, and Government of Karnataka.

The following projects were completed by iMTech student groups as a part of lab courses conducted in HiDES lab in the mentioned semesters.

Currently Trending

Ajay, and Nithin's work on "Tactile sensors engineering for visually impaired education" got accepted in 2019 IEEE Sensors Conference to be held in Montreal, Cannada.

Pranav's work on "Design and development of an autonomous in-seat passenger state identification in a modern vigilance enabled public transportation system" got accepted in ICVES 2019 conference to be held in Cairo, Egypt.

Alan Israel (IMT2015) presented his work on "A dual threshold voltage modified dynamic power cutoff technique to consolidate leakage and speed in a VLSI subsystem" in 2019 IEEE CONECCT conference, held on 26th July, Bangalore, India.

Dr. Madhav Rao presented a paper titled "Design of a non-invasive pulse rate controlled deep vein thrombosis prophylaxis lower limb device" in 41st EMBC conference on 26th July in Berlin, Germany.

Vinay Chandrasekhar secured prestigious S N Bose fellowship to do summer internship in a US university.

Vinay Chandrasekhar is doing summer internship in Prof. Ebrahimi's Bio-Electronics lab at Penn State University.

Pranav Kedia was invited to do summer internship in Prof. Arpita's Robotics lab at IIT-Bombay.

Aravind Reddy was invited for summer internship in the University of Alabama at Tuscaloosa in Professor Sazonov's lab in the Electrical and Computer Engineering department.

Our paper on Development of design models for nanomagnetic logic based combinatorial subsystem got accepted in 19th IEEE Nanotechnology Conference 2019.


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Last updated: Aug-13-2019 by Madhav Rao)

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