Sakshi Arora

Analog ICs, PMICs, Open-source Analog ICs, Neuromorphic Circuits, Hardware for Mental Health

Published / Accepted

1. A. S. Khan and S. Arora, “EEG-Backed Evaluation of Minimal HRV Features for Reliable Stress Detection,” International Conference on Biomedical Engineering and Technology (ICBET), Bali, Indonesia, June 12–15, 2026.
2. A. Patil, N. Verma, P. Borah, A. S. Khan, and S. Arora, “Stress Detection from Consumer-Grade ECG Device Using GA Optimization and Segment-Wise Analysis,” BIOSIGNALS 2026: International Conference on Bio-Inspired Systems and Signal Processing, full paper (12 pages), oral presentation.
3. O. Gavandi and S. Arora, “5.05-nA I_q, 1-mA I_load Self-Biased Cascoded Output-Capacitorless (SBC-OCL) LDO for NB-IoT Applications,” IEEE Dallas Circuits and Systems Conference (DCAS), 2026.
4. Nitheesh M., Prasanna N., and S. Arora, “A PSRR Peak-Suppressed Cascaded LDO Achieving −140 dB PSRR with 10-µA Quiescent Current for Biomedical Sensing Applications,” IEEE Dallas Circuits and Systems Conference (DCAS), 2026.
5. N. Mupalla, O. V. Gavandi, and S. Arora, “Design methodology and automation of a three-stage, OCL LDO with –100 dB PSRR, 3.45 µA I_q, and 800 µA–150 mA I_load,” IEEE Design Methodologies Conference (DMC), Arkansas, USA, 2025.
6. S. Arora and R. R. Manikandan, “PSRR-aware gₘ/I_d-based LDO design with load-capacitance and quiescent-current optimization,” IEEE International Women in Technology Conference (WINTECHCON), Bengaluru, India, 2025.
7. S. Arora and R. R. Manikandan, “Performance-specific, technology look-up-table-based design methodology for low-dropout voltage regulators (LDOs),” Tutorial at 28th IEEE VLSI Design and Test Symposium (VDAT), Vellore, India, 1 Sept 2024.
8. S. Sampath, A. Damale, S. Arora, and R. R. Manikandan, “Design and automation methodology of a wideband, high-PSRR LDO using device look-up tables,” IEEE Design Methodologies Conference (DMC), Grenoble, France, 2024.
9. S. Arora, D. K. Su, and B. A. Wooley, “A compact 120-MHz 1.8 V/1.2 V dual-output DC–DC converter with digital control,” Proc. IEEE Custom Integrated Circuits Conference (CICC), San Jose, California, USA, 2013.

Submitted / Under Review

10. S. T., T. Bhagat, D. Mahawar, S. Arora, J. Bapat, and A. Mishra, “Genetic algorithm-based emulator for mmWave IRS unit cell circuit design,” submitted to IEEE International Conference on Communications (ICC), 2026.
11. S. S. Yadavalli, Shreeya H., and S. Arora, “Automatic gₘ/I_d LDO Designer,” submitted to ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), 2026.
12. R. Komaragiri Sai Vishwanath, R. Rohit, and S. Arora, “A Self-Biased Ultra-Low-Power LDO with Load-Adaptive Quiescent Current for IoT Applications,” submitted to ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), 2026.

VLS 502: Analog IC design, IIIT, Bangalore, 2024-25
VLS 804: Analog Power ICs, IIIT, Bangalore. 2024-25
EE 292P: Power Management IC Design, Stanford University, Fall, 2013 and Fall, 2014

Analog ICs, PMICs, Open-source Analog ICs, Neuromorphic Circuits, Hardware for Mental Health

Industry-University Effort: ADEC: Analog Design Evolution Collective

• Stanford Graduate Felowship awarded in 2010
• Analog Devices Outstanding Student Designer Award