Pranesh Santikellur

Upcoming / Recent (2026)

P. Santikellur, A. Dutta and R. S. Chakraborty, “HPC-VAD: Hardware Performance Counter based Side-channel Analysis for Voice Activity Detection in Automatic Speech Recognition using Multi-scale Signed Recurrence Plots,” Accepted in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2026.  (Accepted)
 

P. Santikellur and R. S. Chakraborty, “Deep Learning for Computational Problems in Hardware Security: Modeling Attacks on Strong Physically Unclonable Function Circuits,” vol. 1052, Springer Nature, 2022.

P. Santikellur, M. Buddhanoy, S. Sakib, B. Ray and R. S. Chakraborty, “A Shared Page-Aware Machine Learning Assisted Method for Predicting and Improving Multi-Level Cell NAND Flash Memory Life Expectancy,” Microelectronics Reliability, vol. 140, p. 114867, 2022.

P. Santikellur and R. S. Chakraborty, “Correlation Integral based Intrinsic Dimension: a Deep Learning Assisted Empirical Metric to Estimate the Robustness of Physically Unclonable Functions to Modeling Attacks,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 10, pp. 3216-3227, Oct. 2022.

S. Chattaopadhyay, P. Santikellur, R. S. Chakraborty, J. Mathew and M. Ottavi, “A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability,” in ACM Transactions on Design Automation of Electronic Systems, vol. 26, no. 6, Article 41, pp. 1-24, Nov. 2021.

P. Santikellur and R. S. Chakraborty, “A Computationally Efficient Tensor Regression Network based Modeling Attack on XOR Arbiter PUF and its Variants,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 6, pp. 1197-1206, June 2021.

V. Govindan, R. S. Chakraborty, P. Santikellur, A. K. Chaudhary, “A Hardware Trojan Attack on FPGA based Cryptographic Key Generation: Impact and Detection,” Journal of Hardware and Systems Security (Springer), vol. 2, no. 3, pp. 225-239, Sep. 2018.

P. Santikellur, R. S. Chakraborty, and J. Mathew, “Hardware Security in the Context of Internet of Things: Challenges and Opportunities,” Internet of Things and Secure Smart Environments: Successes and Pitfalls, 2020, p. 64.

P. Santikellur, R. S. Chakraborty, S. Bhunia, “Hardware IP Protection Using Register Transfer Level Locking and Obfuscation of Control and Data Flow,” in: Katkoori, S., Islam, S.A. (eds), Behavioral Synthesis for Hardware Security, Springer, Cham, 2022.

P. Santikellur, R. Mukherjee, and R. S. Chakraborty, “APUF-BNN: An Automated Framework for Efficient Combinational Logic Based Implementation of Arbiter PUF through Binarized Neural Network,” in Proceedings of the 2021 on Great Lakes Symposium on VLSI (GLSVLSI ’21), Association for Computing Machinery, New York, NY, USA, pp. 89-94, 2021.  (Best Paper Nominated)

P. Santikellur, Lakshya, S. R. Prakash and R. S. Chakraborty, “A Computationally Efficient Tensor Regression Network based Modeling Attack on XOR Arbiter PUF,” IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), pp. 1-6, 2019.

V. S. Balijabudda, D. Thapar, P. Santikellur, R. S. Chakraborty and I. Chakrabarti, “Design of a Chaotic Oscillator based Model Building Attack Resistant Arbiter PUF,” IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), pp. 1-6, 2019.

U. Chatterjee, P. Santikellur, R. Sadhukhan, V. Govindan, D. Mukhopadhyay and R. S. Chakraborty, “United We Stand: A Threshold Signature Scheme for Identifying Outliers in PLCs,” Late Breaking Results (LBR) track of IEEE/ACM Design Automation Conference (DAC), Las Vegas, Nevada, USA, 2019.