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Assistant Professor
anuj [dot] verma [at] iiitb [dot] ac [dot] in
Education : Ph.D. (IIT Mandi)
Anuj Verma is an Assistant Professor in the Department of Electronics and Communication Engineering (ECE) at IIIT Bengaluru. He received his Ph.D. in VLSI Design from the Indian Institute of Technology (IIT) Mandi, where his research focused on developing hardware-efficient algorithms and VLSI architectures for advanced channel decoders targeting 5G and beyond (B5G) wireless communication systems.
Prior to joining IIIT Bengaluru, he worked as a Chief Engineer at Samsung Research Institute, Bengaluru (SRIB), gaining valuable industry experience in hardware design and development for advanced image processing and real-world applications.
His research interests focus on advanced digital VLSI architectures for next-generation communication and intelligent systems. His work focuses on the design and optimization of a high-throughput and energy-efficient channel decoders for 5G/B5G/6G standards, along with hardware–software co-design of AI accelerators for edge intelligence. He is particularly interested in reconfigurable and scalable architectures, algorithm–architecture co-design, and design space exploration for efficient real-time signal processing. His research also extends to ASIC/FPGA prototyping, RTL-to-silicon implementation, and system-level integration aligned with modern modem and SoC design practices.
Research Interests
My research lies at the intersection of VLSI architecture, hardware acceleration, communication systems, and intelligent edge computing, with a focus on designing high-performance, energy-efficient, and reconfigurable digital systems for next-generation computing and communication platforms.
My primary research interests include:
1. Reconfigurable VLSI Architectures
Design and implementation of reconfigurable hardware architectures for communication and signal processing systems, focusing on area-efficient and high-throughput architectures for multi-standard applications.
2. Advanced Channel Decoding Architectures
Development of hardware-efficient architectures for LDPC, Polar, and next-generation error-correcting decoders for beyond-5G/6G communication systems, emphasizing throughput, latency, and energy optimization.
3. RISC-V Based Domain-Specific Architectures
Design of RISC-V based custom processors and accelerators for domain-specific applications such as image processing, edge intelligence, embedded computing, and wireless systems
4. AI-Assisted Communication Hardware
Application of machine learning techniques in communication hardware, particularly for adaptive channel decoding, error prediction, and performance-aware hardware optimization.
5. Post-Quantum Cryptographic Hardware
Efficient hardware architectures for post-quantum cryptographic algorithms, focusing on secure and lightweight implementations for future secure communication systems.
Journal Publications:
- Anuj Verma and Rahul Shrestha, "High-Throughput and Hardware-Efficient ASIC-Chip Fabrication of Reconfigurable LDPC/Polar Decoder for mMTC and URLLC 5G-NR Applications," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 9, pp. 4284-4297, Sept. 2024 (Link).
- Anuj Verma and Rahul Shrestha, "Low Computational-Complexity SOMS-Algorithm and High-Throughput Decoder Architecture for QC-LDPC Codes," in IEEE Transactions on Vehicular Technology, vol. 72, no. 1, pp. 66-80, Jan. 2023 (Link).
- Anuj Verma and Rahul Shrestha, "Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 8, pp. 2835-2839, Aug. 2021 (Link).
Conference Publications:
- Anuj Verma and Rahul Shrestha, "A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, Seville, Spain, 2020 (Link).
- Anuj Verma and Rahul Shrestha, "A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio," 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), pp. 1-6, Bangalore, India, 2020 (Link).
- August – December 2025: HLS & Optimization of Digital Circuits.
- January – April 2026: Physical Design of ASICs.
- Reviewer Journal: IEEE TCAS-I, IEEE TCAS-II, IEEE TVLSI.
- Reviewer Conference: IEEE ISCAS, IEEE MWSCAS, IEEE APCCAS
- Best Thesis Awarded in the IEEE flagship 2025 38th International Conference on VLSI Design & 25th International Conference on Embedded Systems.
- Spot Awarded in the Samsung Research Institute Bengaluru (SRIB).